With increasing integration of semiconductor memory devices, there is a high probability that a failure occurs during a fabrication process of semiconductor cells. This may cause the reduction in yield. In general, although a semiconductor memory device has a small number of failed memory cells, the semiconductor memory device may not be shipped as a product.
In order to reduce the occurrence of failure due to high integration of semiconductor memory devices, a variety of repair methods have been proposed. Representative examples of the repair methods may include a fuse cutting method using laser and an electrical fuse cutting method using a high voltage.
FIG. 1 is a flow chart showing a known repair method for changing a failed cell into a normal cell.
Referring to FIG. 1, the repair method for changing a failed cell into a normal cell may comprise a repair method using fuse cutting in a wafer state and perform a repair method using electrical fuse cutting after packaging.
First, a wafer test entry step S1 is to enter a test for testing a memory cell in which a failure occurs in a wafer state. A repair determination step S2 is to determine whether the failed memory cell checked through the test can be repaired or not. A failure decision step S3 comprises deciding a wafer having a memory cell which was determined to be unrepairable in the repair determination step S2, as a failed wafer, without performing a repair. A fuse cutting step S4 is to perform fuse-cutting using laser only on the wafer which was determined to be repairable in the repair determination step S2 and replace the failed memory cell with a normal memory cell. A wafer test termination step S5 is to terminate the wafer test because the failed memory cell has been replaced with a normal memory cell in the fuse cutting step S4.
A packaging step S6 is to package a wafer having normal memory cells. A package test entry step S7 is to verify whether a failure has occurred while a heat treatment process or the like is performed in the packaging step S6. A repair determination step S8 is to perform a test and discriminate a package in which a failure occurred and a package in which no failure occurred. An electrical fuse cutting step S9 is to replace a failed memory cell with a normal memory cell by performing electrical fuse cutting on the package in which a failure occurred during the package step S6. A test termination step S10 is to terminate the test so as to ship the package having no failure and the package repaired in the electrical fuse cutting step S9.
As such, the repair is performed by the fuse cutting method and the electrical fuse cutting method, in order to repair a failed chip into a normal chip.
In the known repair method, however, a plurality of fuses are provided to perform the fuse cutting method, and an electrical fuse circuit and a high voltage generation circuit are provided to perform the electrical fuse cutting method. Therefore, this configuration increases the layout area of the semiconductor memory device. Furthermore, the fuse cutting method and the electrical fuse cutting method do not allow two or more programming operations. Accordingly, it is impossible to repair a failure which occurs while a user uses an integrated circuit.